How to define multipurpose (i32/f32) register in an LLVM backend? -

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i'd define register multipurpose float , integer register on llvm back-end. know how that?

thanks!

i believe see how implemented in llvm backend architecture familiar with. example, arm has 32 d-registers (d0..d31) can hold either double float or vector values. in case registerclass definition quite straightforward:

// scalar double precision floating point / generic 64-bit vector register class. def dpr : registerclass<"arm", [f64, v8i8, v4i16, v2i32, v1i64, v2f32], 64,                         (sequence "d%u", 0, 31)> {   // allocate non-vfp2 registers d16-d31 first.   let altorders = [(rotl dpr, 16)];   let altorderselect = [{ return 1; }]; }

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