vhdl - Converting 8 bit binary to BCD value -

i have spent countless hours on , decided need help..so here am.

basically doing taking 8 bit input adc , converting value bcd dsiplay on 7 segment board. here code far:

library ieee ; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_unsigned.all;  entity voltage_lut   port ( scaled_value : in  unsigned(7 downto 0);          true_value : out  std_logic_vector (15 downto 0)   ); end voltage_lut;  architecture behavioral of voltage_lut    function  divide  (a : unsigned; b : unsigned) return unsigned     variable a1 : unsigned(a'length-1 downto 0):=a;     variable b1 : unsigned(b'length-1 downto 0):=b;     variable p1 : unsigned(b'length downto 0):= (others => '0');     variable : integer:=0;   begin     in 0 b'length-1 loop       p1(b'length-1 downto 1) := p1(b'length-2 downto 0);       p1(0) := a1(a'length-1);       a1(a'length-1 downto 1) := a1(a'length-2 downto 0);       p1 := p1-b1;       if(p1(b'length-1) ='1')         a1(0) :='0';         p1 := p1+b1;       else         a1(0) :='1';       end if;     end loop;     return a1;   end divide;    signal  adj: unsigned(7 downto -2);    --adjusted max 90   signal  max_value: unsigned(7 downto 0):= "11111111" ;    --adjusted max 90   signal  msb_int: integer;   -- integer form of msb   signal  lsb_int: integer;    --integer form of lsb   signal  adj2: unsigned(15 downto 0);    --converted adjusted integer binary   signal  lsb: std_logic_vector (3 downto 0);    --bcd lsb   signal  msb: std_logic_vector (3 downto 0);    --bcd msb   signal  off: std_logic_vector (3 downto 0):="1010";    --defined segment off   signal  v: std_logic_vector (3 downto 0):="1011";    --defined letter v  begin    adj <= divide ( scaled_value , max_value );   adj2 <= adj* "00001001" ;  end behavioral;     

essentially doing taking 8 bit value adc expressing fraction of max value ( 9) , have convert bcd... when running code getting error stating:

line 38: index value <-2> out of range [0:2147483647] of array

i need answer of division binary number (with decimals eg 11001.110) accurate when multiply 9...

the offending line is:

signal  adj: unsigned(7 downto -2); 

the type unsigned not support negative ranges. if want treat result fixed-point value fractional component, have couple choices, including:

• if have vhdl-2008 compliant tools, can use ieee.fixed_pkg, includes type ufixed, does support negative indices, tried unsigned.

• if don't have vhdl-2008 compliant tools, can manage binary point virtually, i.e. declare:

  signal  adj: unsigned(9 downto 0); 

  with method, need bookkeeping manually, unfortunately. since appear doing multiplies , divides, don't have worry aligning binary point, though. whether value "accurate" or not depends on how use in subsequent logic.