fpga - SV Compilation error: Unexpected token integer -

i compiling below system verilog code in active-hdl9.1 simulator. when compile error

error: vcp2000 tb_hutil.sv : (35, 15): syntax error. unexpected token: integer[_integer]. expected tokens: 'constraint'.

package hutil_pkg;  `define date "june_2012"  `ifdef tbid  `else    `define tbid "rapidio2_testbench"  `endif    `ifdef author  `else    `define author "altera"  `endif      `define info     32'h00000001  `define debug    32'h00000002  `define warning  32'h00000004  `define failure  32'h00000008    static integer err_cnt;          //line no.35 //error on line

i don't understand error , no idea whether problem system verilog syntax or tool issues.

in posted example endpackage missing. use `ifndef if not defined statments.

example below compiles on eda playground:

package hutil_pkg; `define date "june_2012" `ifndef tbid   `define tbid "rapidio2_testbench" `endif  `ifndef author   `define author "altera" `endif  `define info     32'h00000001 `define debug    32'h00000002 `define warning  32'h00000004 `define failure  32'h00000008  static integer err_cnt;   endpackage